FPGA内部dcm输出的100MHZ时钟输出到dsp368的一个时钟引脚上,为什么会出错呢?怎眼才能解决?ERROR:Place:1136 - This design contains a global buffer instance,,driving the net,,that is driving thefollowing (first 30) non-clock lo
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![FPGA内部dcm输出的100MHZ时钟输出到dsp368的一个时钟引脚上,为什么会出错呢?怎眼才能解决?ERROR:Place:1136 - This design contains a global buffer instance,,driving the net,,that is driving thefollowing (first 30) non-clock lo](/uploads/image/z/8925427-19-7.jpg?t=FPGA%E5%86%85%E9%83%A8dcm%E8%BE%93%E5%87%BA%E7%9A%84100MHZ%E6%97%B6%E9%92%9F%E8%BE%93%E5%87%BA%E5%88%B0dsp368%E7%9A%84%E4%B8%80%E4%B8%AA%E6%97%B6%E9%92%9F%E5%BC%95%E8%84%9A%E4%B8%8A%2C%E4%B8%BA%E4%BB%80%E4%B9%88%E4%BC%9A%E5%87%BA%E9%94%99%E5%91%A2%3F%E6%80%8E%E7%9C%BC%E6%89%8D%E8%83%BD%E8%A7%A3%E5%86%B3%3FERROR%3APlace%3A1136+-+This+design+contains+a+global+buffer+instance%2C%2Cdriving+the+net%2C%2Cthat+is+driving+thefollowing+%28first+30%29+non-clock+lo)
FPGA内部dcm输出的100MHZ时钟输出到dsp368的一个时钟引脚上,为什么会出错呢?怎眼才能解决?ERROR:Place:1136 - This design contains a global buffer instance,,driving the net,,that is driving thefollowing (first 30) non-clock lo
FPGA内部dcm输出的100MHZ时钟输出到dsp368的一个时钟引脚上,为什么会出错呢?怎眼才能解决?
ERROR:Place:1136 - This design contains a global buffer instance,
,driving the net,,that is driving the
following (first 30) non-clock load pins.
< PIN:i_VPORT/clock_o.D; >
This is not a recommended design practice in Spartan-6 due to limitations in
the global routing that may cause excessive delay,skew or unroutable
situations.It is recommended to only use a BUFG resource to drive clock
loads.If you wish to override this recommendation,you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue.
< PIN "dcm_u/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
我按照这个提示在UCF中增加了这个约束后,虽然不报错了,但是测量时钟引脚的频率不对.怎么做约束才能让这个引脚从FPGA输出100Mhz的时钟信号?
FPGA内部dcm输出的100MHZ时钟输出到dsp368的一个时钟引脚上,为什么会出错呢?怎眼才能解决?ERROR:Place:1136 - This design contains a global buffer instance,,driving the net,,that is driving thefollowing (first 30) non-clock lo
加了这个约束只是不报这个问题,但并没有解决.你将时钟输出的pin映射到clk管脚输出吧,FPGA中有专门的时钟输出输入管脚,这些和内部时钟网络相连接,具有较小的skew和delay.